María Jesús Garzarán

Curriculum Vitae

Office: 4308
Department of Computer Science
University of Illinois
Thomas M. Siebel Center for Computer Science
201 N. Goodwin
Urbana, IL 61801-2302 USA
(217) 244-8878
garzaran at cs.uiuc.edu
http://polaris.cs.uiuc.edu/~garzaran

· Research interests · Education · Employment · Awards ·
· Publications · Teaching · Other Instructional Activities · Short Courses · Graduate Students · Research funding ·
· Invited talks · Conference talks · By-invitation workshops · Departamental service ·
· Seminar organization · Workshop organization, Chair ·
· Conference organization, Program Committee · Other professional service ·

Research interests

Parallel computer architecture, thread-level speculation, compilers, interaction between hardware and software, and reliability.

Education

1994-2002	Ph.D. in Computer Science and Engineering Systems, Universidad de Zaragoza (Spain), July 2002 Dissertation: Hardware Prefetch, Reduction Support, and Speculative State Buffering in Shared Memory Multiprocessors Advisor: Víctor Viñals
1992-1993	Last year of the engineering studies, option Computer Science , Ecole Nationale Supérieure des Télécommunications de Bretagne (France). These studies were done with a Eramus Fellowship from the European Union. This grant promotes the mobility of the european students.
1987-1993	M.S. in Computer Science, Universidad Politécnica de Valencia (Spain), July 1993. Dissertation: Router pour Chirvan-Bloc Advisor: Louis Olivier Donzelle and Anne Gerodolle

Employment

Since 2005	Research Assistant Professor in the Computer Science Department, University of Illinois at Urbana-Champaign
2002-2005	Research scientist with the Polaris research group in the Computer Science Department, University of Illinois at Urbana-Champaign Supervisor: David Padua
1999-2002	Visiting Scholar with the Illinois Aggressive COMA research group in the Computer Science Department, University of Illinois at Urbana-Champaign.
1993-2002	Lecturer, Computer Science and Engineering Systems Department, Universidad de Zaragoza, Spain.
3/1993-9/1993	Co-Op Intern, France Telecom Research and Development Center in Grenoble, France. Study of VLSI routers for analog circuits

Awards and honors

2003	Best Phd Thesis Award, Universidad de Zaragoza, Spain. This award is given to the top Phd theses of the year at Universidad de Zaragoza.
1992	Erasmus Fellowship from the Universidad Politénica de Valencia, Spain.
1992	Bancaja Fellowship for studying abroad.

Conference Proceedings, Journals, Book Chapters and Workshops

2008

LCPC [ PDF ]
Alexandre Duchateau, Albert Sidelnik, María Jesús Garzarán, and David Padua. P-RAY: A Suite of Micro-benchmarks for Multi-core Architectures. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, July 2008.

SAMOS Workshop [ PDF ]
James Brodman, Basilio Fraguela, María Jesús Garzarán, and David Padua. Design Issues in Parallel Array Languages for Shared Memory. In the 8th International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop), July 2008.

NSF Next Generation Software [ PDF ]
Jing Yu, María Jesús Garzarán, and Marc Snir. Efficient Software Checking for Fault Tolerance. In the Next Generation Software Workshop, in conjunction with IPDPS, April 2008.

NSF Next Generation Software [ PDF ]
Brian A. Garber, Dan Hoeflinger, Xiaoming Li, María Jesús Garzarán, and David Padua. Generation of a Parallel Sorting Algorithm. In the Next Generation Software Workshop, in conjunction with IPDPS, April 2008.

PPoPP [ PDF ]
Jia Guo, Ganesh Bikshandi, Basilio Fraguela, María Jesús Garzarán, and David Padua. Programming with Tiles. To appear in the Proc. of the International Symposium on Principles and Practice of Parallel Programming, 2008. Acceptance ratio 25%.

2007

LCPC [ PDF ]
Jing Yu, María Jesús Garzarán, and Marc Snir. Techniques for Efficient Software Checking. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, October 2007. Acceptance ratio 47%.

NSF Next Generation Software [ PDF ]
Xiaoming Li, María Jesús Garzarán, and David Padua. Optimizing Sorting with Machine Learning Algorithms. In the Next Generation Software Workshop, in conjunction with IPDPS, April 2007.

2006

LCPC [ PDF ][ PRESENTATION ]
Ganesh Bikshandi, Jia Guo, Christoph von Praun, Gabriel Tanase, Basilio B. Fraguela, María Jesús Garzarán, David Padua, and Lawrence Rauchwerger. Design and Use of htalib -- a library for Hierarchically Tiled Arrays. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, November 2006.

Handbook of Parallel Computing [ PDF ]
María Jesús Garzarán, Basilio B. Fraguela and David Padua. Array Constructs for Parallel Programming. Invited paper in Handbook of Parallel Computing: Models, Algorithms and Applications. Editors: Sanguthevar Rajasekaran and John Reif. To appear.

Science of Computer Programming [ PDF ]
Albert Cohen, Sebastien Donadio, María Jesús Garzarán, Cristoph Herrmann, Oleg Kiselyov, and David Padua. In search of a program generator to implement generic transformations for high-performance computing. Science of Computer Programming, Volume 62, Issue 1, pages 25-46, Septemter 2006. Special issue of the first MetaOcaml Workshop 2004.

NSF Next Generation Software [ PDF ]
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheorghe Almasi, Basilio Fraguela, María Jesús Garzarán, David Padua, and Christoph von Praun. Hierarchically Tiled Arrays for Parallelism and Locality. In the Workshop on Performance Engineering Technology and Research Sponsored under the NSF Next Generation Software Program, in conjunction with IPDPS, April 2006.

PPoPP [ PDF ]
Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheorghe Almasi, Basilio Fraguela, María Jesús Garzarán, David Padua, and Christoph von Praun. Programming for Parallelism and Locality with Hierarchically Tiled. In the Proc. of the International Symposium on Principles and Practice of Parallel Programming, pages 48-57, March 2006. Acceptance ratio 27%.

2005

LCPC [ PDF ]
Xiaoming Li and María Jesús Garzarán. Optimizing Matrix Multiplication wit a Classifier Learning System. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, October 2005.

LCPC [ PDF ]
Sebastien Donadio, James Brodman, Thomas Roeder, Kamen Yotov, Denis Barthou, Albert Cohen, María Jesús Garzarán, David Padua and Keshav Pingali. A Language for the Compact Representation of Multiples Program Versions. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, October 2005.

LCPC [ PDF ]
Arkady Epshteyn, María Jesús Garzarán, Gerald Dejong, David Padua, Gang Ren, Xiaoming Li, Kamen Yotov and Keshav Pingali. Analytic Models and Empirical Search: A Hybrid Approach to Code Optimization. In the Proc. of the International Workshop on Languages and Compilers for Parallel Computing, October 2005.

ACM TACO [ PDF ]
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors. In the ACM Transactions on Architecture and Code Optimization (TACO), Volume 2, Number 3, pages 247 - 279, September 2005.

CGO [ PDF ]
Xiaoming Li, María Jesús Garzarán, and David Padua. Optimizing Sorting with Genetic Algorithms. In Proc. of the International Symposium on Code Generation and Optimization, pages 99-110, March 2005. Acceptance ratio 34%.

Proceedings of the IEEE [ PDF ]
Kamen Yotov, Xiaoming Li, Gang Ren, María Jesús Garzarán, David Padua, Keshav Pingali, and Paul Stodghill. Is Search Really Necessary to Generate High-Performance BLASs? In Proceedings of the IEEE, special issue on "Program Generation, Optimization, and Platform Adaptation", Volume 23, Number 2, pages 358 - 386, February 2005.

2004

LCR [ PDF ]
Basilio B. Fraguela, Jia Guo, Ganesh Bikshandi, María Jesús Garzarán, Gheorghe Almasi, Jose Moreira, and David Padua. The Hierarchically Tiled Arrays Programming Approach. In Proc. of Seventh Workshop on Languages, Compilers and Run-Time Support for Scalable Systems, October 2004.

Workshop MetaOCaml [ PDF ]
Albert Cohen, Sebastien Donadio, María Jesús Garzarán, Cristoph Herrmann, and David Padua. In Search for a Program Generator to Implement Generic Transformations for High-Performance Computing. In First MetaOCaml Workshop, October 2004.

LCPC [ PDF ]
Ganesh Bikshandi, Basilio B. Fraguela, Jia Guo, María Jesús Garzarán, Gheorghe Almasi, Jose Moreira, and David Padua. Implementation of Parallel Numerical Algorithms Using Hierarchically Tiled Arrays. In Proc. of the International Workshop on Languages and Compilers for Parallel Computing, September 2004. Also in Lecture Notes in Computer Science 3602. Editors: Rudolf Eigenmann, Zhiyuan Li and Samuel P. Midkiff, pages 87-101, Springer-Verlag, August 2005. ISBN 3-540-28009-X.

CGO [ PDF ]
Xiaoming Li, María Jesús Garzarán, and David Padua. A Dynamically Tuned Sorting Library. In Proc. of the International Symposium on Code Generation and Optimization, pages 111-124, March 2004. Acceptance ratio 31%.

2003

LNCS [ PDF ]
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Software Logging under Speculative Parallelization. Chapter in High Performance Memory Systems. Editors: Haldun Hadimioglu, David Kaeli, Jeffrey Kuskin, Ashwini Nanda, and Josep Torrellas, pages 181-193, Springer-Verlag, November 2003. ISBN 0-387-00310-X.

LCPC [ PDF ]
Jia Guo, María Jesús Garzarán, and David Padua. The Power of Belady's Algorithm in Register Allocation for Long Basic Blocks. In Proc. of the International Workshop on Languages and Compilers for Parallel Computing, October 2003. Also in Lecture Notes in Computer Science 2958. Editor: Lawrence Rauchwerger, pages 374-389, Springer-Verlag, 2004. ISBN 3-540-21199-3.

PACT [ PDF ]
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. In Proc. of the International Conference on Parallel Architectures and Compilation Techniques, pages 170-181, September 2003. Acceptance ratio 17%.

PLDI [ PDF ]
Kamen Yotov, Xiaoming Li, Gang Ren, Michael Cibulskis, Gerald DeJong, María Jesús Garzarán, David Padua, Keshav Pingali, Paul Stodghill, and Peng Wu. A Comparison of Empirical and Model-driven Optimization. In Proc. of the International Conference on Programming Language Design and Implementation, pages 63-76, June 2003. Acceptance ratio 22%.

HPCA [ PDF ]
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors. In Proc. of the Int. Symp. on High-Performance Computer Architecture, pages 191-202, February 2003. Acceptance ratio 22%.

2002

NSF Next Generation Software [ PDF ]
F. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy Amato, Lawrence Rauchwerger, and Josep Torrellas. SmartApps, an Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. In Workshop on Performance Engineering Technology and Research Sponsored under the NSF Next Generation Software Program, in conjunction with IPDPS, April 2002.

2001

PACT [ PDF ]
María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Lawrence Rauchwerger, and Josep Torrellas. Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors.In Proc. of the International Conference on Parallel Architectures and Compilation Techniques, pages 243-254, September 2001. Acceptance ratio 21%.

ISCA [ PDF ]
Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, and Josep Torrellas. Architectural Bottlenecks to the Scalability of Speculative Parallelization. In Proc. of the 28th Annual Int. Symp. on Computer Architecture, pages 204-215, July 2001. Acceptance ratio 15%.

WMPI [ PDF ]
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Software Logging under Speculative Parallelization. In Workshop on Memory Performance Issueshold in conjunction with ISCA, July 2001. An Extended version of this paper appears in a chapter of the Lecture Notes of Computer Science series.

Euro-PDP [ PDF ]
María Jesús Garzarán, José Luis Briz, Pablo Ibáñez, and Víctor Viñals. Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. In Proc. of the Euromicro Workshop on Parallel and Distributed Processing , pages 345-354, February 2001. Acceptance ratio 40%.

1999

JPAR [ PDF ]
María Jesús Garzarán, José Luis Briz, Pablo Ibáñez, and Víctor Viñals. Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. In IX Jornadas de Paralelismo, Spain. September 1999.

1998

ICS [ PDF ]
Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán. Characterization and Improvement of Load/Store Cache-based Prefetching. In International Conference on Supercomputing, pages 369-376, July 1998. Acceptance ratio 47%.

1997

JPAR [ PDF ]
María Jesús Garzarán, Víctor Viñals, José Luis Briz, and Alfredo Orio. Caracterización del Tráfico en Protocolos de Coherencia Snoopy. In VIII Jornadas de Paralelismo, Spain. September 1997.

Technical Reports

DIIS TR RR-02-04
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Software Logging for Multi-version Buffering under Speculative Parallelization. DIIS Technical Report RR-02-04. University of Zaragoza (SPAIN), March 2002.

CSRD TR 1581
María Jesús Garzarán, Milos Prvulovic, Joséa Marí Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. Buffering State with Software Logging in Scalable Speculative Parallelization. CSRD Technical Report 1581. University of Illinois, July 2000.

CSRD TR 1582
Ye Zhang, Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, and Josep Torrellas. A Framework for Speculative Parallelization in Distributed Shared-Memory Multiprocessors. CSRD Technical Report 1582. University of Illinois, July 1999.

Teaching

At the Computer Science Department at the University of Illinois at Urbana-Champaign.

Undergraduate Courses

Spring 08

CS 231: Computer Architecture I

Graduate Courses

Fall 07	CS 498: Program Optimization. This course counts on INTEL experts Paul Petersen and Arch Robison to cover a few lectures on performance tools and parallel programming.
Fall 06	CS 498: Program Optimization
Fall 05	CS 498: Program Optimization

At the Computer Science and Engineering Systems Department , at Universidad de Zaragoza, Spain
Graduate Courses

Spring 95,96,97,98,99,01,02 Computer Networks. Computer Science Master Program
Spring 98,99 Architecture and Microprocessor Technology. Computer Science and Engineering Systems PhD Program

Undergraduate Courses

Spring 01,02 Computer Architecture-I
Spring 01,02 Computer Architecture-I
Fall 95,96,97,98,00,01 Communication Networks for Computers

Spring 95,96,97,98 Introduction to Computer Networks

Fall 98 Computer Architecture for Engineers

Fall 98 Parallel architectures Laboratory

Fall 94 Computer Architecture Laboratory

Spring and Fall 94 Programming Introduction and Laboratory

Spring and Fall 94 Computer Architecture for engineers

Senior Projects Supervised (At the Computer Science and Engineering Systems Department , Universidad de Zaragoza, Spain)

ATM by Satellite. Luis Montesano del Campo. February 1999.

Simulation and Behavior of Coherence Protocols. Alfredo Orio. July 1998.

Study of the Consistency Implementation in http through Invalidation Using IP Multicast. Jorge Bernad Pelegrin. December 1997.

Investigation of the UPC (Usage Parameter Control) in ATM. Marta Esteva. September 1997.

Other Instructional Activities

Preliminary Examination Committees

Xiaoming Li (2005)
Ganesh Bikshandi (2005)
Jia Guo (2006)
Jing Yu (2007)

Short Courses

Short course (20 hours) on "Program Optimization", at Universidad de Zaragoza, Spain, June 2006.

Graduate Students

PhD students co-advised

Xiaoming Li, 2006.
First Job: Assistant Professor, Department of Electrical and Computer Engineering, University of Delaware.
Thesis: "Machine Learning Techniques for Code Generation and Optimization".

Currently co-advising 4 PhD students:

James Brodman

Jing Yu

Albert Sidelnik

Alexandre X. Duchateau

Master students co-advised:

Brian Garber (2006)
Thesis: "The Necessity of Tuning To Achieve Top Performance Parallel Sorting Algorithms".

Currently co-advising 1 Ms students:

Dan Hoeflinger

Research funding

2007

$900K NSF CSR-AES lead PI: Josep Torrelas. num Pis from UIUC: 3 (Maria J. Garzaran and David Padua). Title: Novel Programming Models and Architectures to Simplify Parallel Programming.

$300K NSF UIUC-Texas A&M. PI: David Padua. num Pis from UIUC: 2 (Maria J. Garzaran). Collaborative Research: Next Generation Compiler for Emerging Multicore Systems

2006

$212K NSF CSR-AES UIUC-Texas A&M, lead PI: Maria J. Garzaran, num Pis from UIUC: 1. Title: SoftCheck: Compiler and Run-Time Technology for Efficient Fault Detection and Correction in Low nm-Scale Multicore Chips.

2005

$800K NSF CSR-AES UIUC-Cornell, lead PI: David Padua, num Pis from UIUC: 5 (Maria J. Garzaran, Luddy Harrison, Jiawei Han, and Gerald DeJong). Title: Library Generation for Advanced Execution Systems.

$12 K cash + $21 K equipment, INTEL. Pis: Maria J. Garzaran and David Padua. Title: Library Generation.

$350 K, DARPA CMU-UIUC-Drexel. Lead PI: Jose Moura (CMU), num Pis from UIUC:2 (David Padua and Maria J. Garzaran). Title: Intelligent HW-SW Compilers for Signal Processing Applications.

2003

$14K, UIUC-CNRS, lead Pi: David Padua. Num pis from UIUC:3 (Maria J. Garzaran and Josep Torrellas). Title: Program Optimization.

$61K equipment, INTEL. Pis: Maria J. Garzaran and David Padua. Title: Library Generation.

Invited talks

Library Generators for Parallel Machines

Dagstuhl workshop on Programming Models for Ubiquitous Parallelism. September 2007.

A Memory Hierarchy Conscious and Self-tunable Sorting Library

IBM TJ Watson Research Center. November 2003.

Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors

Architecture seminar at the Computer Science and Electrical & Computer Engineer Departments, University of Illinois. October 2003.
Computer Science Department, Texas A&M University, May 2003.

Buffering State with Software Logging in Scalable Speculative Parallelization

Compiler seminar at the Computer Science Department at the University of Illinois. October 2003.
Center for Simulation of Advanced Rockets at the University of Illinois. August 2000.
IBM TJ Watson Research Center. July 2000.

Conference and workshop presentations

Software Checking for Fault Tolerance
Next Generation Software Workshop, concurrently with the IEEE International Parallel and Distributed Processing Symposium (IPDPS), Miami, April 2008
Adaptive Sorting.
Workshop on Automatic Tuning of Libraries and Applications, concurrently with High Performance Computer Science Week (HPCSW), Denver, Colorado, April 2008
Programming for Parallelism and Locality with Hierarchically Tiled Arrays.
Meeting of the Midwest Society for Programming Languages and Systems (MSPLS), University of Illinois at Urbana-Champaign, April 2006.
Optimizing Sorting with Genetic Algorithms.
Workshop on Compilers for Parallel Computers (CPC), La Coruña, January 2006.
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation.
Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), New Orleans, September 2003
Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors.
Int. Symp. on High-Performance Computer Architecture (HPCA), Anaheim, February 2003.
Architectural Support for Parallel Reductions in Scalable Shared Memory Multiprocessors.
Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), Barcelona, September 2001.
Software Logging under Speculative Parallelization.
Workshop on Memory Performance Issues (WMPI) concurrently with Intl. Symp. on Computer Architecture, Gothenburg, Sweden, June 2001.
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
Euromicro Workhop on Parallel and Distributed Processing (Euro-PDP01), Mántova, Italy, February 2001.
Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
IX Jornadas de Paralelismo (JPAR), Murcia, Spain, September, 1999.
Caracterización del Tráfico en Protocolos de Coherencia Snoopy.
VII Jornadas de Paralelismo (JPAR) , Cáceres, Spain, September 1997.

Departmental service

Departmental committees:

Industrial Affiliates Committee 2005.

By-invitation Workshops

Adaptive Library Workshop I organized by Intel, Chicago, September 2005.
Adaptive Library Workshop II organized by Intel, Oregon, April 2006.

Seminar Organization

Co-organizer of the seminar: Programming Models for Ubiquitous Parallelism , September 2007, Dagsthul, Germany.

Workshop Organization, Chair

Program Co-Chair: Workshop on Languages and Compilers for Parallel Computing, 2007 (LCPC 2007) .
Program Co-Chair: Workshop on Programming Models for Ubiquitous Parallelism, held in conjuction with PACT 2006, Seattle, Washington, September 2006.

Conference Organization, Program Committee

HotPar 2009: Workshop on Hot Topics in Parallelism
IPDPS 2009: International Parallel & Distributed Processing Symposium.
ICSOFT 2008: International Conference on Software and Data Technologies.
HiPC 2007: International Conference on High Performance Computing.
IPDPS 2007:International Parallel & Distributed Processing Symposium.
LCPC 2006, 2007, and 2008: International Workshop on Languages and Compilers for Parallel Computing.
HPCC 2006: Conference on High Performance Computing and Communications.

Other Professional Service

Participant in NSF Proposal Evaluation Panel, October 2006.
Reviewer for
- CGO 2007, 2008: International Conference on Code Generation and Optimization
- CC 2006: Journal on Concurrency and Computation: Practice and Experience
- PACT 2003, 2005, 2006: International Conference on Parallel Architectures and Compilation Techniques
- ICS 2003, 2005: International Conference on Supercomputing
- Euro-Par 2005
- PPoPP 2005, 2007 : ACM Symposium on Principles and Practices of Parallel Programming
- TPDS 2003, 2004, 2007, and 2008: IEEE Transactions on Parallel and Distributed Systems
- JPDC 2003, 2006: Journal of Parallel and Distributed Computing
- HPCA 2001, 2002, and 2003: International Symposium on High Performance Computer Architecture
- IPDPS 2002, 2003, and 2006 : International Parallel and Distributed Processing Symposium.
- ICPP 2000, and 2002: International Conference on Parallel Processing
- ISCA 2001: International Symposium on Computer Architecture

Spring 95,96,97,98,99,01,02	Computer Networks. Computer Science Master Program
Spring 98,99	Architecture and Microprocessor Technology. Computer Science and Engineering Systems PhD Program

Spring 01,02	Computer Architecture-I
Spring 01,02	Computer Architecture-I
Fall 95,96,97,98,00,01	Communication Networks for Computers
Spring 95,96,97,98	Introduction to Computer Networks
Fall 98	Computer Architecture for Engineers
Fall 98	Parallel architectures Laboratory
Fall 94	Computer Architecture Laboratory
Spring and Fall 94	Programming Introduction and Laboratory
Spring and Fall 94	Computer Architecture for engineers