• ATM by Satellite. Luis Montesano del Campo. February 1999.
• Simulation and Behavior of Coherence Protocols. Alfredo Orio. July 1998.
• Study of the Consistency Implementation in http through Invalidation Using IP Multicast. Jorge Bernad Pelegrin. December 1997.
• Investigation of the UPC (Usage Parameter Control) in ATM. Marta Esteva. September 1997.

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Other Instructional Activities

• Xiaoming Li (2005)
• Ganesh Bikshandi (2005)
• Jia Guo (2006)
• Jing Yu (2007)
• James Brodman(2009)
• Aaron Becker (2011)
• Alexandre Duchateau (2011)
• Osman Sarood (2012)
• Albert Sidelnik (2012)
• Xing Zhou (2012)
• Ehsan Totoni (2013)
• Saeed Maleki (2014)

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Short Courses and Tutorials.

• Short course (20 hours) on "Program Optimization", at Universidad de Zaragoza, Spain, June 2006.
• UPCRC Illinois Summer School on Multicore Programming, at University of Illinois at Ubana-Champaign, June 2009. Support for data parallelism through language Ct and Implicit Parallelism.
• UPCRC Illionis Summer School on Multicore Programming, at University of Illinois at Urbana-Champaign, July 2010. Course on Vectorization.
• Tutorial on Program Optimization through Loop Vectorization:
  • Supercomputing, November 2010. New Orleans, Luisiana.
  • Code Generation Optimization (CGO), April 2011. Chamonix, France.
  • Program Language Design and Implementation (PLDI), June 2011. San Jose, California.
  • Short course (20 hours) on Multicore programmig, at Universidad de Zaragoza, Spain, July 2013.

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Graduate Students

• Jing Yu, 2008.
  First Job: Google.
  Thesis:"Effective Software Checking for Fault Tolerance".
• James Brodman, 2010.
  First Job: Intel.
  Thesis:"Data Parallelism with Hierarchially Tiled Objects".
• Xing Zhou, 2013
  Firt Job: Google.
  Thesis: "Tiling Optimization for Stencil Computations".
• Albert Sidelnik, 2013.
  First Job: NVidia.
  Thesis: "Compilation Techniques and Language Support to Facilitate Dependence-Driven Computation".
  
• Saeed Maleki, 2015.
  First Job: Microsoft Research.
  Thesis: "Communication Avoiding Algorithms for Amorphous Problems".
  

• Brian Garber (2006)
  Thesis: "The Necessity of Tuning To Achieve Top Performance Parallel Sorting Algorithms".
• Dan Hoeflinger (2008)
  Thesis: "Automatic Tuning of a Sorting Library for Multicore Systems".
• Swapnil Ghike (2012)
  Thesis: "Effectiveness of Program Transformations and Compilers for Directive-based GPU Programming Models".
• Danqing Xu (2014)
  Thesis: "Optimization by Runtime Specialization for Sparse Matrix-Vector Multiplication".
• Luis Remis (2016)
  Thesis: "Breadth-first Search for Social Network Graphs on Heterogeneous Platforms

• Konstantinos Karantasis.

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Research funding

2015

• $600K NSF lead PI: David Padua. num Pis from UIUC: 2. Title: Advancing Autovectorization

2013

• $500K NSF lead PI: Maria J. Garzaran. num Pis from UIUC: 2. Title: Scripting at the Speed of C.

2011

• $1,052 K NSF lead PI: David Padua. num Pis from UIUC: 2. Title: Kali: A System for Sequential Programming of Multicore Processors.

2010

• $486K NSF SHF lead PI: Sam Kamin. num Pis from UIUC: 3 (Maria J. Garzaran and Vikram Adve). Title: Run-Time Program Generation and Empirical Optimization.

• NSF Passionate on Parallel Research Experiences for Undergraduates

2007

• Intel and Microsoft Universal Parallel Computing Research Center
• $900K NSF CSR-AES lead PI: Josep Torrelas. num Pis from UIUC: 3 (Maria J. Garzaran and David Padua). Title: Novel Programming Models and Architectures to Simplify Parallel Programming.
• $300K NSF UIUC-Texas A&M. PI: David Padua. num Pis from UIUC: 2 (Maria J. Garzaran). Collaborative Research: Next Generation Compiler for Emerging Multicore Systems

2006

• $212K NSF CSR-AES UIUC-Texas A&M, lead PI: Maria J. Garzaran, num Pis from UIUC: 1. Title: SoftCheck: Compiler and Run-Time Technology for Efficient Fault Detection and Correction in Low nm-Scale Multicore Chips.

2005

• $800K NSF CSR-AES UIUC-Cornell, lead PI: David Padua, num Pis from UIUC: 5 (Maria J. Garzaran, Luddy Harrison, Jiawei Han, and Gerald DeJong). Title: Library Generation for Advanced Execution Systems.
• $12 K cash + $21 K equipment, INTEL. Pis: Maria J. Garzaran and David Padua. Title: Library Generation.

2003

• $14K, UIUC-CNRS, lead Pi: David Padua. Num pis from UIUC:3 (Maria J. Garzaran and Josep Torrellas). Title: Program Optimization.
• $61K equipment, INTEL. Pis: Maria J. Garzaran and David Padua. Title: Library Generation.

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Invited talks

• EuroMPI, Chicago, September 2017.

• Intel, Santa Clara, April 2014.
• Huawei, Santa Clara, April 2014.
• Qualcomm, Santa Clara, April 2014.
• NVidia, Santa Clara, April 2014.

• Fifth Workshop of the Joint Laboratory for Petascale Computing, Champaign, November 2013.

• At Department of Computer Science, University of Chicago, June 2013

• At School of Computing, University of Utah. April 2013.
• At School of Electrical and Computing Engineering, Purdue University. April 2013.
• At Computer Architecture Department, Universitat Politecnica de Catalunya. May 2013.

• At Computer Science and Engineering, Universidad de Zaragoza, Spain, July 2012.

• New Abstractions for Data Parallel Programming, First Workshop of the Joint Laboratory for Petascale Computing, Paris, June 2009.

• Autotuning, UPCRC Intel-Microsoft seminar, December 2008.

• Dagstuhl workshop on Programming Models for Ubiquitous Parallelism. September 2007.

• IBM TJ Watson Research Center. November 2003.

• Architecture seminar at the Computer Science and Electrical & Computer Engineer Departments, University of Illinois. October 2003.

• Computer Science Department, Texas A&M University, May 2003.

• Compiler seminar at the Computer Science Department at the University of Illinois. October 2003.

• Center for Simulation of Advanced Rockets at the University of Illinois. August 2000.

• IBM TJ Watson Research Center. July 2000.

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Conference and workshop presentations

• Easy, Fast, and Energy-efficient Object Detection on Heterogeneous On-chip Architectures. High-Performance Embedded Architectures and Compilers (HiPEAC), January 2014

• Programming for Locality and Parallelism with Hierarchically Tiled Arrays. MiniSymposium on New Abstractions for Linear Algebra for Parallel Architectures, in conjunction with the 14th SIAM Conference on Parallel Processing for Scientific Computing, Seattle, February 2010.

• A Detector for Harmful Errors
  IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), San Francisco, March 2009.

• Software Checking for Fault Tolerance
  Next Generation Software Workshop, concurrently with the IEEE International Parallel and Distributed Processing Symposium (IPDPS), Miami, April 2008

• Adaptive Sorting.
  Workshop on Automatic Tuning of Libraries and Applications, concurrently with High Performance Computer Science Week (HPCSW), Denver, Colorado, April 2008

• Programming for Parallelism and Locality with Hierarchically Tiled Arrays.
  Meeting of the Midwest Society for Programming Languages and Systems (MSPLS), University of Illinois at Urbana-Champaign, April 2006.

• Optimizing Sorting with Genetic Algorithms.
  Workshop on Compilers for Parallel Computers (CPC), La Coruña, January 2006.

• Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation.
  Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), New Orleans, September 2003

• Tradeoffs in Buffering Multi-Version Memory State for Speculative Thread-Level Parallelization in Multiprocessors.
  Int. Symp. on High-Performance Computer Architecture (HPCA), Anaheim, February 2003.

• Architectural Support for Parallel Reductions in Scalable Shared Memory Multiprocessors.
  Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), Barcelona, September 2001.

• Software Logging under Speculative Parallelization.
  Workshop on Memory Performance Issues (WMPI) concurrently with Intl. Symp. on Computer Architecture, Gothenburg, Sweden, June 2001.

• Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
  Euromicro Workhop on Parallel and Distributed Processing (Euro-PDP01), Mántova, Italy, February 2001.

• Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
  IX Jornadas de Paralelismo (JPAR), Murcia, Spain, September, 1999.

• Caracterización del Tráfico en Protocolos de Coherencia Snoopy.
  VII Jornadas de Paralelismo (JPAR) , Cáceres, Spain, September 1997.

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Departmental service

• Industrial Affiliates Committee 2005.

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By-invitation Workshops

• Adaptive Library Workshop I organized by Intel, Chicago, September 2005.

• Adaptive Library Workshop II organized by Intel, Oregon, April 2006.

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Seminar Organization

• Co-organizer of the seminar: Programming Models for Ubiquitous Parallelism , September 2007, Dagsthul, Germany.

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Workshop Organization

• Program Co-chair: First International Workshop on Communication Optimizations in High Performance Computing (COMHPC), held in conjuction with SC 2016, Salt Lake City, Utah, November 2016.

• Program Co-Chair: Workshop on High Performance Scripting Languages, held in conjunction with PPoPP 2015, San Francisco, February 2015.

• Program Co-Chair: Workshop on Languages and Compilers for Parallel Computing, 2007 (LCPC 2007).

• Program Co-Chair: Workshop on Programming Models for Ubiquitous Parallelism, held in conjunction with PACT 2006, Seattle, Washington, September 2006.

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Conference Organization

• EuroPar 17 Global Chair of Topic 8: "Parallel and distributed programming, interfaces and languages".
• SC 14, Program Co-Chair (Area of Programming Systems), Supercomputing.

• PACT 2013, 2015, 2016, 2017, and 2018, International Conference on Parallel Architectures and Compilation Techniques.

• CC 2016, International Conference on Compiler Construction.

• ASPLOS 2016, International Conference on Architectural Support for Programming Languages and Operating Systems.

• SC 2015, Supercomputing, Area of Programming Systems.

• ICS 2015, International Conference on Supercomputing.

• PPoPP 2015, 2017, International Symposium on Principles and Practices of Parallel Programming.

• HiPEAC 2014, 2015, International Conference on High-Performance and Embedded Architectures and Compilers.

• SBAC-PAD 2013, and 2014, International Symposium on Computer Architecture and High Performance Computing.

• IPDPS 2007, 2009, 2013, 2014, and 2015: International Parallel & Distributed Processing Symposium.

• HiPC 2013, International Conference on High Performance Computing.

• CGO 2012 and 2018, International Conference on Code Generation and Optimization.

• PMEA 2011, International Workshop on Programming Moels for Emergins Architectures (PMEA 2011), in conjunction with PACT 2011.

• IWOMP 2011, International Workshop on OpenMP.

• WEHA 2010, Workshop on Exploitation of Hardware Accelerators, in conjunction with the International Conference on High Performance Computing and Simulation (HPCS 2010).

• Automated Program Generation for Computational Science 2010, in conjunction with International Conference on Computational Science (ICCS).

• MULTIPROG 2010: Workshop on Programmability Issues for Multi-Core Computers, in conjunction with the High-Performance and Embedded Architectures and Compilers (HiPEAC).

• SMART 2010: Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion.

• Micro 2009: IEEE/ACM International Symposium on Microarchitecture

• HotPar 2009: Workshop on Hot Topics in Parallelism

• iWAPT 2009: International Workshop on Automatic Performance Tuning.

• ICSOFT 2008: International Conference on Software and Data Technologies.

• STMCS 2007: Workshop on Software Tools for Multi-Core Systems, in conjunction with CGO.

• HiPC 2007 and 2013: International Conference on High Performance Computing.

• LCPC 2006, 2007, 2008, and 2009: International Workshop on Languages and Compilers for Parallel Computing.

• HPCC 2006: Conference on High Performance Computing and Communications.

• CGO 2011: Publications and Students Chair for International Conference on Code Generation and Optimization
• CGO 2012: Judge of the ACM Student Research Competition, CGO 2012.
• PPoPP 2016: Publications Chair for International Symposium on Principles and Practice of Parallel Programming.

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Other Professional Service

• Participant in NSF Proposal Evaluation Panel, October 2006, October 2008, March 2009, February 2011, March 2011, May 2013, April 2016.
• Editorial Board Member for the Encyclopedia on Parallel Computing with Springer Verlag.



• External Reviewer Committee Member for
  • PLDI 2014: International Conference on Programming Language Design and Implementation.

  • PPoPP 2012, 2013, and 2014: International Symposium on Principles and Practice of Parallel Programming.

  • ASPLOS 2012, 2014, 2015, and 2017: International conference on Architectural Support for Programming Languages and Operating Systems.

• Reviewer for
  • Microprocessor and Microsystems 2010: Microprocessors and Microsystems, Elsevier.

  • PPoPP 2005, 2006, 2010, 2011: International Symposium on Principles and Practice of Parallel Programming.

  • HiPEAC 2010: International Confere on High-Performance Embedded Architectuers and Compilers.

  • CGO 2007, 2008: International Conference on Code Generation and Optimization

  • CC 2006, 2009, 2011: Journal on Concurrency and Computation: Practice and Experience

  • PACT 2003, 2005, 2006: International Conference on Parallel Architectures and Compilation Techniques

  • ICS 2003, 2005: International Conference on Supercomputing

  • Euro-Par 2005

  • TPDS 2003, 2004, 2007, 2008, 2010, 2011: IEEE Transactions on Parallel and Distributed Systems

  • JPDC 2003, 2006, 2011: Journal of Parallel and Distributed Computing

  • HPCA 2001, 2002, and 2003: International Symposium on High Performance Computer Architecture

  • IPDPS 2002, 2003, and 2006 : International Parallel and Distributed Processing Symposium.

  • ICPP 2000, and 2002: International Conference on Parallel Processing

  • ISCA 2001: International Symposium on Computer Architecture