Some of the I-ACOMA Publications
Architecture and Systems:
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Executing Sequential Binaries on a Multithreaded
Architecture with Speculation Support
by Venkata Krishnan and Josep Torrellas,
Workshop on Multi-Threaded
Execution, Architecture and Compilation (MTEAC'98), January 1998.
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A Clustered Approach to Multithreaded Processors
by Venkata Krishnan and Josep Torrellas,
International Parallel Processing Symposium, March 1998.
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Cache-Only Memory Architectures
by Fredrik Dahlgren and Josep Torrellas,
Submitted for publication, January 1998.
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Hardware for Speculative Run-Time Parallelization
in Distributed Shared-Memory Multiprocessors
by Ye Zhang, Lawrence Rauchwerger, and Josep Torrellas,
Fourth International Symposium on High-Performance Computer Architecture,
February 1998.
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Enhancing Memory Use in Simple Coma:
Multiplexed Simple Coma
by Sujoy Basu and Josep Torrellas,
Fourth International Symposium on High-Performance Computer Architecture,
February 1998.
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How Processor-Memory Integration Affects the Design of DSMs
by Liuxi Yang, Anthony-Trung Nguyen, and Josep Torrellas,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember,
June 1997.
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Efficient Use of Processing Transistors for Larger On-Chip Storage:
Multithreading
by Venkata Krishnan and Josep Torrellas,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember,
June 1997.
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The Memory Performance of DSS Commercial Workloads
in Shared-Memory Multiprocessors
by Pedro Trancoso, Josep-L. Larriba-Pey, Zheng Zhang, and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture,
January 1997.
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Reducing Remote Conflict Misses:
NUMA with Remote Cache versus COMA
by Zheng Zhang and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture,
January 1997.
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Speeding up the Memory Hierarchy in Flat COMA Multiprocessors
by Liuxi Yang and Josep Torrellas,
Third International Symposium on High-Performance Computer Architecture,
January 1997.
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The Illinois Aggressive Coma Multiprocessor Project (I-ACOMA)
by Josep Torrellas and David Padua,
6th Symposium on the Frontiers of Massively Parallel Computing, October 1996.
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An Efficient Implementation of Tree-Based Multicast Routing for
Distributed Shared-Memory Multiprocessors
by Manuel Perez Malumbres(*), Jose Duato(*), and Josep Torrellas,
(* Universidad Politecnica de Valencia).
1996 Symposium on Parallel and Distributed Processing, October 1996.
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Comprehensive Hardware and Software Support for
Operating Systems to Exploit MP Memory Hierarchies
by Chun Xia and Josep Torrellas,
Submitted for publication, 1996.
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The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding
by Pedro Trancoso and Josep Torrellas,
1996 International Conference on Parallel Processing, August 1996.
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Instruction Prefetching of Systems Codes With Layout Optimized for
Reduced Cache Misses
by Chun Xia and Josep Torrellas,
23rd International Symposium on Computer Architecture, June 1996.
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Optimizing the Primary Cache for Parallel Scientific
Applications: The Pool Buffer Approach
by Liuxi Yang and Josep Torrellas,
1996 International Conference on Supercomputing, June 1996.
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Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors
by Alain Raynaud, Zheng Zhang, and Josep Torrellas,
Second International Symposium on High-Performance Computer Architecture,
January 1996.
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Improving the Data Cache Performance of Multiprocessor Operating Systems,
by Chun Xia and Josep Torrellas,
2nd International Symposium on High Performance Computer
Architecture, January 1996.
- Data Forwarding in Scalable Shared-Memory Multiprocessors,
by D. A. Koufaty, X. Chen, D. K. Poulsen, and J. Torrellas,
1995 International Conference on Supercomputing, July 1995.
Extended Version in IEEE Transactions on Parallel and
Distributed Systems, December 1996.
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Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory
Binding and Group Prefetching,
by Zheng Zhang and Josep Torrellas,
22nd International Symposium on Computer Architecture, June 1995.
- Optimizing Instruction Cache Performance for Operating System Intensive
Workloads,
by Josep Torrellas, Chun Xia and Russell Daigle,
1st International Symposium on High Performance Computer Architecture, January
1995.
Extended Version To appear in IEEE Transactions on Computers, 1996.
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Low Perturbation Address Trace Collection
with Simple Hardware Performance Monitors,
by Russell Daigle, Chun Xia, and Josep Torrellas,
Submitted for publication to a Journal, 1995.
- The Performance of the Cedar Multistage Switching Network,
by Josep Torrellas and Zheng Zhang,
Supercomputing'94, November 1994.
Extended Version in IEEE Transactions on Parallel and
Distributed Systems, April 1997.
- An Efficient Algorithm for the Run-time Parallelization of DOACROSS Loops,
by Ding-Kai Chen, David Oesterreich, Josep Torrellas and Pen-Chung Yew,
Supercomputing'94, November 1994.
Extended Version Submitted to a Journal, 1995.
- Comparing the Performance and Programmibility of the DASH and Cedar
Multiprocessors for Scientific Loads,
by Josep Torrellas and David Koufaty, and David Padua,
1994 International Conference on Parallel Processing, August 1994.
Extended Version Submitted to a Journal, 1995.