The current superscalar approach to exploit ILP is giving
diminishing returns. Alternate design approaches include simultaneous
multithreading (SMT) and multiple processors on a single chip(CMP).
Unlike the CMP approach, the centralized SMT avoids wasting resources when
a thread stalls due to some hazard. However, with bypass delays being critical,,
any centralized (be it SMT or a conventional superscalar) scheme may slow
down the clock frequency. An intuitive solution is to distribute or cluster
the SMT architecture on the lines of the CMP architecture.
We have studied the performance of parallel applications
(user- and compiler-parallelized) on a clustered SMT architecture and shown
that the clustering has minimal impact on performance in terms of raw IPC,
without taking into consideration the cycle time advantage of the clustered
over the centralized SMT.
Our ongoing work focuses on improving the performance
of sequential binaries on the above multithreaded architectures (SMT or
CMP). We use a hardware/software approach that enables even sequential
binaries (without the need for re-compilation) to execute on these multithreaded
architectures. The software support includes a compiler that can analyze
and annotate binaries to enable execution in multithreaded mode. The hardware
includes support for inter-thread register communication/synchronization
as well as handling memory dependences.
Publications:
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Venkata Krishnan and Josep Torrellas, Hardware and Software
Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor,
12th ACM International Conference on Supercomputing (ICS), July 1998.
Abstract
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Venkata Krishnan and Josep Torrellas, A
Clustered Approach to Multithreaded Processors, 12th International
Parallel Processing Symposium (IPPS), March 1998.
Abstract
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Venkata Krishnan and Josep Torrellas, Executing
Sequential Binaries on a Multithreaded Architecture with Speculation Support,
Workshop on Multi-Threaded Execution, Architecture and
Compilation (MTEAC'98), January 1998. Abstract
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Venkata Krishnan and Josep Torrellas, Efficient
Use of Processing Transistors for Larger On-Chip Storage: Multithreading,
Workshop on Mixing Logic and DRAM: Chips that Compute and Remember,
June 1997.Abstract
